1. Field of the Invention
This invention generally relates to integrated circuit (IC) and liquid crystal display (LCD) fabrication and, more particularly, to a CMOS inverter circuit enabled through the use of vertical TFTs (V-TFTs) configured in a multi-planar layout.
2. Description of the Related Art
The size of TFTs formed in liquid crystal display (LCD) processes are limited by the resolution of large panel photolithography tools. Currently, the resolution of feature sizes is about 0.5 microns (um) and larger. High-speed circuit operation requires a TFT capable of high drive current and low parasitic capacitance. These characteristics are obtained by shrinking the device size, especially the transistor channel length. For example, conventional production CMOS technology uses transistor channel lengths of 90 nanometers (nm), and lower, for very high-speed operation.
FIGS. 1A and 1B are a schematic drawing and a plan view, respectively, of a conventional inverter circuit (prior art). The most basic logic element is an inverter, consisting of an N and P channel transistor as shown in FIG. 1A. A common arrangement for fabrication of an inverter circuit uses planar transistors is shown in FIG. 1B. These transistors have a channel length (L) equal to 0.8 microns. Note that the width of the P channel device is larger than the N channel device because of the higher drive current of N channel transistors. In most cases the P/N width ratio is about 2.
The above-mentioned Related Application discloses a V-TFT with a very short channel length. It would be advantageous if the size of simple CMOS circuits, such as an inverter, could be made smaller using V-TFTs.
It would be advantageous if the size of an inverter circuit could be made smaller, with a more compact topology, by taking advantage of the non-planar features of the V-TFT.